The present invention relates to digital circuits, particularly to digital circuits employed in memory devices in which an unstable clock signal, used to time certain memory operations, is transferred into a stable clock domain.
It is well known to use an internal master clock signal MCLK in memory devices to time many internal operations which must be performed by the memory device. One of these operations is the enabling of entry data and data clock paths into the memory device. FIG. 1 illustrates the input paths for the data DQ and data clock DCLK signals. As illustrated, the data signal paths DQxc3x8 . . . DQ17 of a memory device are connected to respective receiver circuits 13 which are enabled by an applied signal RXEN. When the data signals are gated through receiver 13 by the signal RXEN, they pass through an adjustable delay device 17, and then into respective latches 19. The data applied to latches 19 are clocked into the memory device by the externally applied data clock signal DCLK. The latter signal is gated by and passes through receiver 21 when it is enabled by the receiver enable signal RXEN.
The DCLK signal, after passing through receiver 21 and delay 23, is applied to the latches 19 to latch the data on the data paths DQxc3x8 . . . DQ17. The data paths also include an output circuit for the memory device which includes output latch 15 which receives a clock signal for clocking data out of the memory device and a buffer 11 which applies the output data onto the respective data paths DQxc3x8 . . . DQ17.
The receiver enable signal RXEN must be received at the receivers 13 and 21 prior to the time that the respective data signals, for receiver 13, and DCLK signal for receiver 21, are received The RXEN signal in turn is generated internally from a master clock signal MCLK which controls all of the internal operations of a memory device. The RXEN signal is generated upon receipt at the memory device of a WRITE command and in response to the next received edge of the MCLK signal. In order to properly control many of the internal operations of the memory device, the timing of the master clock signal MCLK is typically adjusted in response to temperature and/or voltage variations within the memory device. This in turn affects the timing of the generation of the signal RXEN.
FIG. 4 illustrates the typical relationship between an arriving DCLK signal and the RXEN signal. As shown, the RXEN signal should occur during a preamble portion of the DCLK signal before the first clock transition xe2x80x9c0xe2x80x9d which is used to latch in data on the data paths DQxc3x8 . . . DQ17 and before a certain additional period of time shown by the crosshatching in FIG. 4, which accommodates signal skew within the memory device. Thus, the receiver enable signal RXEN must occur before a period of time denoted as t1 in FIG. 4.
In cases of large variations in the timing of MCLK, there will also be corresponding large variations in the timing of the receiver enable signal RXEN as shown by the double headed arrow in FIG. 4. It is possible in such cases that the RXEN signal is not generated sufficiently in advance of the time t1 which may cause clocking transitions 0, 1, 2, 3 of DCLK to be incorrectly applied to the latch 19 relative to the data incoming on the data paths DQxc3x8 . . . DQ17. This may cause improper operation of the memory device. It would be preferable if the RXEN signal were not subject to the timing variations which occur with signal MCLK.
The present invention provides a memory device and its method of operation in which the RXEN signal does not vary in response to variations in the signal MCLK. Instead, a clock edge of the MCLK signal which is used to generate the RXEN signal is associated with a clock signal which is derived from an externally received clock signal related to DCLK. The association is such that an edge of the MCLK signal which is used to generate the RXEN signal is placed at approximately the center of a pulse of the clock signal derived from the externally applied clock signal. The clock signal derived from the externally applied signal is then used to generate a new RXENxe2x80x2 signal. Since the signal derived from the externally applied signal is always stable and does not move with variations in voltage and/or temperature as does the signal MCLK or the prior signal RXEN, the timing of the newly generated receiver enable signal is also stable and does not move in response to variations in voltage and/or temperature.